Design of Single Error Correction-Double Adjacent Error Detection-Triple Adjacent Error Detection-Tetra Adjacent Error Detection (Sec-Daed-Taed- Tetra Aed) Codes

Error correction codes are used in semiconductor memories to protect information against soft and hard errors. Soft error is a major concern for memory reliability especially for memories that are used in space applications. Hamming codes are attractive as they are simple to construct for any word length and encoding / decoding can be done with low latency. In this paper, the design of Single Error Correction-Double Adjacent Error Detection-Triple Adjacent Error Detection-Tetra Adjacent Error Detection (SEC-DAED-TAED-Tetra AED) codes through bit placement algorithm is presented with less number of parity bits. In conventional (Error detection and Correction) EDC mechanism, Single Error Correction and Double Error Detection (SEC-DAED) are done by using Hamming Code. In order to detect the Triple adjacent error in SEC-TAED, it is required to add one parity bit, which consumes more amount of computational time for detecting the triple adjacent error. In Tetra adjacent error in SEC-Tetra AED is also required to add one more parity bit for detecting the error. To overcome this problem, SEC-DAED-TAEDTetra AED method is proposed in this paper. In proposed, Tetra Adjacent Error Detection does not require the parity bits to detect the errors. In conventional SEC-Tetra adjacent error detection, it is performed by bit placement algorithm in our proposed work which offers more efficiency. The combined structure of SEC-DAED-TAED-Tetra AED is used to transfer the information for performing the space communication. It is more efficient and high speed compared to conventional method.